1. Field of the Invention
This invention relates to sequential circuits and similar circuits, more specifically to the sequential circuits and the like using ferroelectrics.
2. Description of the Related Art
Latch circuits and flip-flop circuits are known generally as sequential circuits. A flip-flop circuit 2 depicted in FIG. 14 is an example of the conventional sequential circuit. FIG. 15 is a timing chart for illustrating the operations of the flip-flop circuit 2 depicted in FIG. 14. The flip-flop circuit 2 comprises a latch circuit 4 (serves as the master latch circuit) and another latch circuit 6 (serves as the slave latch circuit) both connected in series. The output of the latch circuit 4 is labeled as "PA" depicted in FIG. 15, that is an output PA shows a signal detected at a point PA shown in FIG. 14.
The latch circuit 4 is turned into the latched-state while turning the latch circuit 6 into the unlatched-state when a clock-pulse Cp becomes "Low" state from "High" state (see FIG. 15(a)). In this way, data corresponding to data Dn (the data provided currently) at the negative edge (High-to-low transition) of the clock pulse Cp (the signal detected at the point PA has a value equivalent to an inverted value of the data Dn) is latched in the latch circuit 4 while outputting the data Dn to an output terminal Q.
Subsequently, the latch circuit 4 is turned into the unlatched-state while turning the latch circuit 6 into the latched-state when a clock-pulse Cp becomes "High" state from "low" state (see FIG. 15(b)). In this way, the data Dn is latched in the latch circuit 6 while outputting the data Dn again to the output terminal Q.
Thereafter, the latch circuit 4 is turned into the latched-state again while turning the latch circuit 6 into the unlatched-state when a clock-pulse Cp becomes "Low" state from "High" state (see FIG. 15(c)). In this way, data corresponding to the data Dn+1 (the data provided subsequently) at the negative edge (high-to-low transition) of the clock pulse Cp (the signal detected at the point PA has a value equivalent to an inverted value of the data Dn) is latched in the latch circuit 4 while outputting the data Dn+1 to the output terminal Q.
As described above, the data thus latched can be outputted within a duration equivalent to one complete cycle of the clock pulse Cp by latching data at the negative edge of the clock pulse Cp as a result of using the flip-flop circuit 2. Consequently, stable outputs without noises can be obtained.
Sequential processings having a high reliability can be performed by using a combination of a plurality of sequential circuits such as the flip-flop circuit 2 and combined circuits such as logical gates.
The conventional sequence circuit such as the flip-flop circuit 2, however, has the following problems to be solved. Adequate voltages must be applied to the circuit all the time in order to hold the data being processed.
Data being processed under sequential processings and that stored in a memory is completely erased when the power supply is shut off by an accident. The data can not be recovered even after the recovery of the power supply. In order to recover the data into the original one just before the accident, another sequential processings must be performed again from its beginning. It consumes much time to perform the sequential processings for every accident, and the data erase cause lack of processing reliability.